1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing techniques and, more particularly, to a technique for planarizing semiconductor wafers.
2. Prior Art
The art is abound with references pertaining to techniques for polishing a surface. Various semiconductor polishing techniques today can be traced back to the polishing methods employed to polish optical lenses. Similar techniques have been utilized in the semiconductor field to polish bare wafers, which are then used as the base substrate for manufacturing integrated circuit devices. Thus, a number of methods are known in the prior art for polishing bare wafers, such as a silicon wafer.
The manufacture of an integrated circuit device requires the formation of various layers (both conductive and non-conductive) above the base substrate to form the necessary components and interconnects. During the manufacturing process, removal of a certain layer or portions of a layer must be achieved in order to pattern and form the various components and interconnects. Generally this removal process is termed "etching" or "polishing."
One of the techniques available for etching is the chemical-mechanical polishing (CMP) process in which a chemical slurry is used along with a polishing pad. The mechanical movement of the pad relative to the wafer provides the abrasive force for removing the exposed surface of the wafer. Because of the broad surface area covered by the pad in most instances, CMP is utilized to planarize a given layer. Planarization is a method of treating a surface to remove discontinuities, such as by polishing (or etching), thereby "planarizing" the surface.
It has been theorized that abrasive material removal from a semiconductor wafer surface requires actual pad-wafer contact for proper CMP to occur. Another theory states that the actual material removal is achieved by the pad pressure on a hydrodynamic layer which is generally the slurry disposed between the wafer and the pad. However, what is known is that the presence of the slurry is required for obtaining optimum results in performing CMP.
A variety of techniques and tools for performing CMP are well-known in the prior art. U.S. Pat. Nos. 4,141,180 and 4,193,226 are just two examples of earlier schemes. After initial usage of CMP in semiconductor planarization, the practice lost ground to other forms of etching. The industry generally favored the usage of dry techniques, such as ion and plasma etching. However, with the advent of larger wafer sizes and smaller sub-micron dimensioned devices being formed on these wafers, CMP is again being viewed in favorable light as one of the preferred techniques available for planarization. U.S. Pat. Nos. 5,245,790 and 5,245,796 are just two examples of more recent interest in the CMP technology.
However, the application of existing CMP tools and methods to the new generation of sub-micron devices has amplified previously known problems or created new ones. Due to the smaller dimensions, including the usage of thinner semiconductor layers, tighter tolerances are now needed. Where certain tolerances were permitted with the older generation devices, these tolerances are no longer acceptable. Additionally it is preferred to obtain process uniformity while performing CMP from one wafer to the next.
A major difficulty with the prior art techniques is in maintaining a consistent combination of even slurry distribution between the wafer and pad along with uniform abrasion of the exposed wafer surface. Because of the difficulty in controlling the amount of slurry present between the wafer and the pad, it is difficult to maintain a steady and consistent control on the planarization process. Although a number of approaches have been devised, such as cutting grooves in the pad, process control is still lacking.
Therefore, it is appreciated that a novel technique for attempting to control and better predict the planarization process parameters is desirable. This is especially true as the technology for developing future generations of memory devices, such as 256 Megabyte and 1 Gigabyte DRAMs and beyond, are exploited. The present invention addresses this need.